1. Field
Exemplary embodiments relate generally to a complementary metal-oxide-semiconductor (CMOS) image sensor (CIS) and, more particularly, to a comparison device using a small sampling capacitor for an input terminal and using a fixed reference voltage and a CMOS image sensor using the same.
Next, in terms used in the following description of embodiments, an input common mode voltage indicates an input common mode voltage of a first comparator that performs a “correlated double sampling (CDS)” operation.
2. Description of the Related Art
In general, in a CMOS image sensor (CIS) using a column-parallel analog-to-digital (ADC) structure, the size of a sampling capacitor positioned at an input terminal of a comparison unit occupies a large part of the entire sensor area.
The characteristics of a correlated double sampling (CDS) operation performed in the comparison unit of the CMOS image sensor may vary significantly depending upon an input common mode voltage, resulting in the degradation of the image quality of the CMOS image sensor.
For example, since a “comparator with single-ended AC-coupled input” uses one input sampling capacitor, it may be implemented to have a small area, but when a swing voltage of a ramp signal is changed according to an analog gain, the input common mode voltage is changed. Such a change in the input common mode voltage serves as a noise source and reduces the linearity of the CMOS image sensor.
In another example, since a “comparator with differential AC-coupled input” operates with a feedback structure, it captures the input common mode voltage by itself. In this case, ramp noise may be reduced by a sampling capacitor to which a ramp signal is inputted, but an area increases because two input sampling capacitors are used.